1. Technical Field
Various embodiments generally relate to a semiconductor device and more particularly, to a design technology for a semiconductor device.
2. Related Art
Recently, various attempts have been made to develop a technology for increasing a net die in order to improve the fabrication costs associated with semiconductor memory devices. As one of the various attempts, a technology for modifying the 8F2 cell array structure into the 6F2 or 4F2 cell array structure has been suggested. Since the 6F2 cell array structure includes a larger number of cells integrated per unit area than the 8F2 cell array, much attention has been directed at the 6F2 cell array structure.
In general, a folded bit line scheme is applied to the 8F2 cell array structure, and an open bit line scheme is applied to the 6F2 cell array structure. The folded bit line scheme refers to a scheme in which a bit line and a bit line bar are formed in parallel to each other along one direction of a sense amplifier. The open bit line scheme refers to a scheme in which a bit line and a bit line bar are spaced from each other at both sides of a sense amplifier.
FIG. 1 is a diagram illustrating a semiconductor device with the open bit line scheme.
Referring to FIG. 1, a cell array CA within a memory cell mat includes a plurality of memory cells MC formed at the respective intersections between a plurality of word lines WL0 to WLn and a bit line pair BL0 and BLB1. The bit line pair BL0 and BLB1 formed in the cell array CA may be coupled to different sense amplifiers positioned at the top and bottom of the cell array CA.
Specifically, among the bit lines BL0 and BLB1, the first bit line BL0 is connected to a sense amplifier SA0 positioned at the top of the cell array CA. The sense amplifier SA0 amplifies the voltage of the memory cell MC through charge sharing with the bit line pair, that is, the first bit line BL0 and the first bit line bar BLB0. The first bit line bar BLB0 is coupled from a cell array within another memory cell mat.
Furthermore, among the bit lines BL0 and BLB1, the second bit line bar BLB1 is coupled to a sense amplifier SA1 positioned at the bottom of the cell array CA. The sense amplifier SA1 amplifies the voltage of the memory cell MC through charge sharing with the bit line pair, that is, the second bit line BL1 and the second bit line bar BLB1. The second bit line BL1 is coupled from a cell array within another memory cell mat.
FIG. 2 is a diagram illustrating the arrangement structure of a conventional memory bank with the open bit line scheme.
Referring to FIG. 2, a plurality of memory cell mats MAT0 to MAT15 are arranged in the memory bank, and sense amplifier blocks S/A_ARRAY0 to S/A_ARRAY15 are arranged between the respective memory cell mats MAT0 to MAT15. In FIG. 2, SA represents a sense amplifier included in the sense amplifier blocks S/A_ARRAY0 to S/A_ARRAY15. FIG. 2 also illustrates bit line pre-charge voltages VBLP.
In the open bit line scheme, the sense amplifier blocks positioned at the top and bottom of each memory cell mat are used in order to sense amplifier data stored in the memory cell mat.
In order for the first sense amplifier block S/A_ARRAY0 to sense and amplify data stored in a part of memory cells within the first memory cell mat MAT0 positioned at one edge of the memory bank, a dummy mat DUM_MAT is formed in the memory bank. That is, the first sense amplifier block S/A_ARRAY0 amplifies data stored in a part of memory cells within the first memory cell mat MAT0 through charge sharing with a bit line pair coupled from the dummy mat DUM_MAT and the first memory cell mat MAT0. The second sense amplifier S/A_ARRAY1 senses and amplifies data of the other memory cells within the first memory cell mat MAT0.
In the 16th memory cell mat MAT15 positioned at the other edge of the memory bank, only data stored in a part of memory cells within the 16th memory cell mat MAT15 are sensed and amplified by the 16th sense amplifier block S/A_ARRAY15, and data stored in the other memory cells within the 16th memory cell mat MAT15 are not sensed and amplified. The reason why no sense amplifier block is arranged at the bottom of the 16th memory cell mat MAT15 is that a bit line pair required for charge sharing is not provided for the corresponding sense amplifier block.
Thus, data which must be stored in the other memory cells of the 16th memory cell mat MAT15 are stored in the above-described dummy mat DUM_MAT, and then sensed and amplified by the first sense amplifier block S/A_ARRAY0. That is, the first sense amplifier block S/A_ARRAY0 amplifies the data stored in the other memory cells within the 16th memory cell mat MAT15 through charge sharing with the bit line pair coupled from the dummy mat DUM_MAT and the first memory cell mat MAT0. For this operation, the same word line address is allocated to the 16th memory cell mat MAT15 and the dummy mat DUM_MAT, and the 16th memory cell mat MAT15 and the dummy mat DUM_MAT are operated at the same time. Therefore, when the 16th memory cell mat MAT15 and the dummy mat DUM_MAT are operated, current consumption is doubled, compared to when another memory cell mat is operated.